The present invention relates generally to the field of electrical circuit testing, and more particularly, to a method and system for displaying boundary scan debugging information.
The testing of electrical circuits is an essential portion of the process involved in the design and manufacture of electrical circuits. The development of a test that is known to run on a known good board is an essential step in setting up manufacturing tests. Once a test is known to be a good test, it may be run on boards under manufacture to accurately identify whether they are passing or failing.
During the development of a test, the test may fail when run on a known good board. The cause of the failed test may be that the test vectors are inaccurate, the netlist information about the board is inaccurate, or the implementation of the test support system in one or more of the board components are not implemented correctly. A need exists for a tool that assists the test engineer in developing a known good test by pinpointing the causes of test failures when running the test on a known good board.
One test that is often developed is known as boundary scan. Boundary scan is a test system in which each component of a circuit to be tested is constructed with a set of shift registers placed between each device pin and with a specific internal logic system. This system has been defined in an Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1-1990. The boundary scan standard allows the entire circuit to be accurately tested by scanning only the boundary pins of the circuit. For a complete description of boundary scan testing, see Parker, Kenneth P., The Boundary Scan Handbook, ISBN0-7923-9270-1 (1992).
To run a boundary scan test requires that the circuit under test include boundary scan functionality. FIG. 1 is a block diagram of a boundary scan component 100. Boundary scan component 100 includes internal logic 106 that is coupled to receive input data via input pins 102 and to output output data via output pins 104. Each input pin 102 and output pin 104 of interest is coupled to a separate boundary cell 110 in a boundary scan register 108. Boundary scan cells 110 are coupled serially in a loop configuration. Boundary scan test pins TDI 112, TCK 114, TDO 116, and TMS 118 are provided as dedicated boundary scan test pins that have the ability to electrically contact bed-of-nails fixture probes. Test Clock (TCK) pin 114 and Test Mode Select (TMS) pin 118 are both coupled to a Test Access Port (TAP), and are used to implement a boundary scan communication protocol. At any given time, Test Data In (TDI) pin 112 and Test Data Out (TDO) pin 116 are each switchably coupled to one of the boundary scan register 108, an instruction register 140, or a bypass register 150.
Boundary scan instruction register 140 is used to set the mode of operation for one or more data registers 150 and 160. When testing one or more specific boundary scan components that are linked in a chain of components, bypass register 150 is used to shorten the chain of cells to a single boundary scan cell through a boundary scan component. The boundary-scan communication protocol, which is also known as the xe2x80x9cJTAGxe2x80x9d (Joint Test Action Group) protocol, is described in detail. in the IEEE/ANSI Standard 1149.1-1990.
In operation, instructions are loaded into instruction register 140 under the control of TMS pin 118 and TCK pin 114 via TDI pin 112. The instruction present in instruction register 140 determines which of boundary scan register 108, data registers 160, or bypass register 150 is coupled between TDI pin 112 and TDO pin 116. Data is shifted into the currently selected register 108, 150, or 160 via TDI pin 112 in synchronization with a clock signal received on TCK pin 114. When data is shifted into cells 110 of boundary scan register 108, the bit values shifted into the cells 110 are seen on the respective pins 102, 104 that the corresponding cells are coupled to. A boundary scan tester (not shown) probes the pins 102, 104 of interest to capture the actual value seen on the pins.
Boundary scan testing is usefull for testing electrical circuits that include multiple cross-connected integrated circuits. In this configuration input signals may be applied to one integrated circuit that lies in a chain of multiple integrated circuits. Boundary scan testing allows the debug engineer to capture values driven by driving nodes and to compare them to the values received by their receiving nodes further down the chain. If the values do not match, this indicates an incorrect wiring or bad connection in the circuit under test.
FIG. 2 is a block schematic diagram of a circuit board that comprises two non-boundary scan components 230 and 240, and two boundary scan components 210 and 220 that are linked together to form one larger boundary scan chain. The chain is formed by connecting the TDO pin 218 of boundary scan component 210 to the TDI pin 226 of boundary scan component 220. Data is shifted serially through the cells in the chain from TDI pin 216 to TDO pin 228, an operation is performed, and the data collected for each cell in the chain is then shifted out of the chain through TDO pin 228. A full set of captured data, referred to herein as a xe2x80x9cframexe2x80x9d, includes a bit value captured for each boundary scan cell in the entire chain. Each frame sequence is shifted serially out of the chain and becomes the actual value data. The position of a bit in a given frame corresponds to the position of its cell number in the chain. Accordingly, the first bit in the frame corresponds to the first boundary scan cell (cell 0, closest to TDO) in the chain, the second bit in the frame corresponds to the second boundary scan cell (cell 1 in the chain) in the chain, and so on. The actual value captured on a given cell in the chain may be extracted by examining the bit in each frame that corresponds to the cell""s position in the chain.
The overall test consists of multiple frames that are all concatenated together end to end in one long serial bitstream. Because boundary scan test data is by nature highly serialized, this means that a sequence of data being placed on a single pin or node during a test is scattered throughout a multitude of other bits. Prior art methods for extracting boundary scan vectors from a lengthy stream of serial bits has involved a process of detecting the beginning of the serialized stream of bits, keeping track of the count of bits received from the serialized stream, generating a set of vectors from the received bits, and matching each of the vectors to a set of predicted vectors. Accordingly, if even a single bit is not detected or is mis-detected, the set of actual vectors may become entirely mis-aligned with the set of predicted vectors when matching up the two sets of vectors.
Accordingly, a need exists for a method and interface for viewing predicted and actual boundary scan test data in aparallel format rather than in the serialized format of the prior art. A need also exists for a method and interface that allows the user to constrain, organize, and sort the test data being viewed to enhance the user""s ability to pinpoint wiring or connect problems.
In accordance with the present invention, a graphical user interface for displaying boundary scan test data, and method for producing the same, is presented. The user interface display allows a user to view boundary scan test data generated by a boundary scan testing device in a format well-suited for debugging. Serial data received from the testing device is organized into a parallel format to, display predicted versus actual data values on a per node basis, to show how a node is passing or failing. In a preferred embodiment, the user views the frame cell number in the boundary scan chain, the device cell number within a device at that point of the chain, the device name, the pin of the device associated with the cell, the node associated with the pin, the predicted value for the cell, the actual value for the cell as it differs from the predicted value if it differs, and the cell numbers for drivers that match predicted and actual data. Frame cells can be displayed in numerical frame order, node name order, failing status only, or passing status only. The preferred embodiment display has the capability to display interesting correlations in the data to assist the user in debugging the circuit under test, including devices driving at fail, devices receiving at fail, devices driving only passes, devices receiving only passes, nodes always failing, nodes sometimes failing, and nodes always passing.